Integrated circuit memory devices continue to increase in integration density and operational speed, as more and more memory cells are integrated in an integrated circuit. In designing highly integrated memory devices, the power distribution in the integrated circuit can impact the integration density and operational speed. For example, the arrangement of power lines and signal lines in one or two layers can impact the integration density and operating speed. If two layers are used, the layer may occupy a smaller area and have a higher operating speed. Moreover, based on the design of the power lines, the power that is supplied to the interior of the integrated circuit may not be sufficient, thereby impacting performance.
A conventional layout of power lines in an integrated circuit memory device will now be described in connection with FIGS. 1-3. For ease of understanding, FIGS. 1-3 illustrate simplified layouts of a Static Random Access Memory (SRAM) integrated circuit device.
FIG. 1 illustrates an equivalent circuit of a conventional SRAM cell. As shown in FIG. 1, the standard SRAM cell MCI includes high resistance load resistors R1 and R2, conventionally made of polysilicon, and a pair of cross-coupled N-channel MOS transistors Q3 and Q4. A pair of N-channel pass transistors, also referred to as transfer transistors, Q1 and Q2 is also included.
As shown in FIG. 1, the load resistors R1 and R2 are coupled between a power supply voltage and a respective drain of transistors Q3 and Q4, to thereby form nodes N1 and N2. The sources of transistors Q3 and Q4 are coupled to a second power supply voltage, generally ground voltage. The gate of transistor Q3 is cross-coupled to node N2 and the gate of transistor Q4 is cross-coupled to the node N1. First transfer transistor Q1 is coupled between a bit line BL and node N1. The gate of transfer transistor Q1 is coupled to word line WL. Second transfer transistor Q2 is coupled between a complementary bit line BL and node N2, with its gate coupled to the word line WL.
As is well known, memory cell MCI stores complementary voltages at nodes N1 and N2. Thus, if the transistors Q1 and Q2 are turned on by an appropriate voltage from word line WL that is supplied by a word line driver coupled to a row decoder, complementary data levels at nodes N1 and N2 are transferred to the bit lines BL and BL respectively. This memory cell is also commonly referred to as a four transistor SRAM cell and is widely used in SRAM devices, such as 128K.times.8 SRAMs.
Referring now to FIG. 2, a layout of transistors Q1-Q4 of FIG. 1 in an integrated circuit will now be described. As shown, the transistor layout is symmetrical with respect to point C and is laid out in an active region 10 of an integrated circuit substrate such as a silicon substrate. Active region 10 is indicated by alternate long and short dashed lines and hatched with oblique lines. As also shown, a gate layer 12 of polysilicon is formed on the active region 10. More specifically, the polysilicon gate layer 12 is divided into four sections that are indicated by dashed lines. The region denoted by reference number 10-N1 in FIG. 2 corresponds to node N1 of FIG. 1. At this region 10-N1 in an active region 10, the drain region Q1d of transistor Q1 and the drain region Q3d of transistor Q3 are formed. As also shown, bit line BL is arranged as a first metal layer on gate layer 12 of transistor Q1. Complementary bit line BL is arranged in the first metal layer on gate layer 12 of transistor Q2. The bit lines BL and BL, indicated by alternating long and short dashed lines, are arranged parallel to each other. The word lines WL are arranged in a second metal layer, on the first metal layer and insulated therefrom. As shown, the word lines WL orthogonally cross the bit lines BL and BL.
In FIG. 2, an arrangement of power lines that provide power supply and ground voltage to the cell is not indicated. The power lines are not indicated because the power lines generally are arranged in a peripheral region outside the memory cell array region in the integrated circuit. This relationship is shown with reference to FIG. 3.
FIG. 3 illustrates a conventional arrangement of an integrated circuit memory device. As shown in FIG. 1, power lines 100 (ground voltage VSS) and 110 (power supply voltage VCC) are conventionally arranged in the second metal layer outside the memory cell array and at opposite ends thereof. As shown, the memory cell array region includes four memory cell array blocks 303A-303D, each of which includes an array of memory cells, corresponding to FIGS. 1 and 2. A row decoder 302A is arranged between the memory cell array blocks 303A and 303B, and another row decoder is arranged between the memory cell array blocks 303C and 303D. Thus, a row decoder is commonly used by two memory cell array blocks and performs a row decoding operation in response to a row address signal that is received from external to the integrated circuit.
Still referring to FIG. 3, the bit lines BL0-BLn are arranged in the first metal layer on each block of the memory cell array region 303. The bit lines extend parallel to the power lines 100 and 110. Word lines WL0-WLn are arranged in the second metal layer on bit lines BL0-BLn and insulated therefrom. The word lines orthogonally cross the bit lines. A respective word line is coupled to a respective polysilicon gate layer 12 of a memory cell in a strapping region via a contact 301.
In operation, an output of the row decoder 302A is transferred to corresponding memory cells via the word lines and the polysilicon gate layers, through the respective contacts 301. This arrangement can reduce the time delay differences between memory cells that are close to and far away from the row decoder 302.
In the layout of FIG. 3, the bit lines are arranged in a first metal layer and the word lines are arranged in a second metal layer. This double metal layer structure can allow the integrated circuit to have higher operating speeds compared to integrated circuits using a single metal layer. However, there is a need to allow a further decrease in integrated circuit size and allow for an increase in speed.